CARD_CLK_GEN_SEL=Val_0x0
SDMMC Status Register 0
| INTCLK_EN | Internal clock request. When this is 0, ACLK and BCLK can be stopped. |
| CLK2CARD_ON | Control to switch on clock supplied to the card |
| CARD_CLK_EN | Card clock PLL enable |
| CARD_CLK_GEN_SEL | Card clock generator mode 0 (Val_0x0): Divided clock mode 1 (Val_0x1): Programmable clock mode |
| CARD_CLK_FREQ_SEL | Card clock frequency select 1 (Val_0x1): 100 MHz 2 (Val_0x2): 50 MHz 4 (Val_0x4): 25 MHz 8 (Val_0x8): 12.5 MHz 16 (Val_0x10): 6.25 MHz 32 (Val_0x20): 3.125 MHz 64 (Val_0x40): 1.56 MHz 128 (Val_0x80): 781.25 kHz 256 (Val_0x100): 390.625 kHz 512 (Val_0x200): 195.312 kHz |